Total reduction of leakage power through combined effect of sleep stack and variable body biasing technique

Leakage power consumption has become a major concern for VLSI circuit designers. Leakage power will become dominant by the year 2020 as per the report of ITRS. I propose the new approach, named sleepy stack with variable body biasing (SSVBB), which reduces the leakage current thereby saving the state of art. It uses traditional sleep transistors which are placed parallel to PMOS/NMOS between the pull up/pull down device and VDD/GND. Dual Vth can be also be applied to reduce sub threshold leakage current. It achieves exact same power reduction as zigzag approach along with saving the logic state of the circuit. Based on the experiments with the inverter as the benchmark circuit, it is found that there is 48% of reduction in delay but with the sacrifice of area. For the application which requires long idle/standby time while maintaining the logic state, the stack sleep with variable body biasing can be used.