Design of energy efficient random access memory circuit using stub series terminated logic i/o standard on 28nm fpga

This paper is based on the designing of energy efficient memory circuit using various IO standard of SSTL logic family on 28nm (Artix-7) Field Programmable Gate Array (FPGA). We are using Xilinx ISE simulator version 14.2, Verilog hardware description language and Artix-7 FPGA. Six different SSTL IO standard are compared with each other to find the most power efficient among them. The design has been tested for power consumption at different operating frequencies as of Intel processor that are at Intel I-3 5005U 2.0 GHz, Intel I-3 5015U 2.1. GHz, Intel I-3 5157U 2.5 GHz, Intel I-5 3380M 2.9 GHz, Intel I-5. 3340U 3.1 GHz and Intel I-7 3370K 3.5 GHz to check the compatibility of the design with processors available in the market and to find most efficient IO standard at different operating frequencies and at two different temperatures i.e. 25°C and 50°C.